Clock-data recovery (CDR) techniques are used to recover both clock and data signals from an incoming data signal. In one prior-art CDR technique, referred to herein as edge-based CDR and illustrated in FIG. 1, a signal receiving circuit samples an incoming data signal at both the midpoint and edges of data eyes (i.e., data valid intervals) to obtain a set of data samples ( . . . Dn−2, Dn−1, Dn, Dn+1, Dn+2, . . . ) and edge samples ( . . . Tn−2, Tn−1, Tn, Tn+1, Tn+2, . . . ), respectively. If the data samples that bound a given edge sample indicate a transition between high and low states, then the edge sample indicates whether the clock edge used to trigger the edge sampling operation occurred early or late relative to the data signal transition, and therefore may be used to adjust the clock phase. Referring to expanded view 75, for example, data samples Dn−1 and Dn are logic ‘0’ and ‘1’ values, respectively, and therefore indicate a rising-edge transition in the incoming data signal. If the edge-sampling clock edge is early relative to the data signal transition, the edge sample will be captured before the data signal crosses decision threshold, DT (i.e., the threshold compared with the incoming signal to resolve the logic state of the edge and data samples), and therefore will have a logic-low (‘0’) state. If the clock edge is late relative to the data signal transition, the edge sample, Tn, will have a logic-high (‘1’) state. Conversely, in a falling-edge transition of the data signal, a logic ‘1’ edge sample indicates an early clock edge, and a logic ‘0’ edge sample indicates a late clock edge. Thus, each edge sample bounded by different-state data samples may be viewed as a vote for either advancing or retarding the edge-sampling clock signal (i.e., the edge clock signal), and the clock phase may be adjusted according to the majority after a number of votes have been received. By this operation, the phase of the edge clock signal is iteratively adjusted to achieve and maintain alignment between transitions of the edge clock signal and edges of the data eyes. The data clock signal (i.e., the clock signal used to trigger data sampling operations) is phase offset from the edge clock signal such that data clock transitions are evenly spaced in time between leading and trailing edge clock transitions, thereby establishing the data sampling point at the midpoint between edges of the data eyes.
While effective in many applications, edge-based CDR yields increasingly non-optimal results as signaling rates approach and exceed the signal path bandwidth. That is, as signaling rates progress deeper into the gigahertz range, data eyes become increasingly compressed and are characterized predominantly by signal path charging and discharging patterns. Referring to FIG. 2, for example, instead of the idealized waveform illustrated in dashed outline, each data eye is opened and closed as exponential charging/discharging waveforms cross the decision threshold, DT. Because the exponential rise and fall time of the signal cross the threshold earlier than the idealized linear transition, edge-based CDR yields edge and data clock alignments that are phase advanced by an amount PD relative to idealized edge and data clock alignments. As a result, while the data clock transitions at the mathematical midpoint between edge clock transitions, the resulting sample point (i.e., yielding Dn), does not necessarily occur at the largest eye opening, but rather occurs at a suboptimal point while the eye opening is still increasing. As the signaling rate is increased, the transition sampling points grow closer together (i.e., the data eye is compressed in time), pushing the edge-based-CDR sampling point further in the lower-magnitude direction, thereby reducing signaling margin and ultimately limiting the data rate of the signaling system.